1. Field of the Invention
This invention relates to a logic circuit, more particularly an emitter coupled logic(ECL) circuit whose operational speed is increased by reducing the discharge time of charges accumulated in a load capacitance while preventing increase of power consumption.
ECL circuits are often used as logic circuits in high performance systems such as large-sized computers, work stations, and measuring instruments due to their high speed characteristics. With recent improvements in system performance, ECL logic circuits are required to be higher in speed and integration density. But the greater the integration, the greater the power consumption and the more the delay in long wiring cannot be ignored. Therefore it is necessary to realize a low power consumption and high-speed operation of the circuit in long wiring.
2. Description of the Related Art
ECL logic circuits are high-speed digital circuits composed of a current made logic (CML) circuit and emitter-follower transistor added to improve the load driving capacity.
To one of the bases of transistors of the CML circuit is input a fixed reference voltage V ref (central voltage value of logical amplitude), which becomes the threshold voltage of the circuit. The output voltage is characterized in that both positive and negative outputs (OR and NOR logical outputs) can be taken out.
Since a wiring load capacitance CL exists at the output side of the ECL logic circuit, the charging and discharging time of charges accumulated in this wiring load capacitance CL is one of the factors determining the circuit operation speed.
If the wiring load capacitance CL is large, it takes the output a longer time to change from the H level to the L level than from L level to the H level.
This means that the time change from the H level to L level and from the L level to H level is unbalanced, causing problems in design, construction, and use.
These problems can be solved by using a circuit which discharges the wiring load capacitance at a low impedance when the output changes from the H level to L level in place of a pull-down resistance or constant current source.
As such a circuit, there is an active pull-down ECL logic circuit as shown in FIG. 1. In FIG. 1, numeral 1 denotes an active pull-down ECL logic circuit (OR/NOR circuit) which consists of the CML circuit (ECL logic part) 2 made of emitter-coupled transistors Q1 and Q2, a constant current transistor Q3, resistors R1, R2, and R3; the emitter-follower circuit 3 made of an emitter-follower transistor Q4, pull-down transistor Q5, and emitter-follower resistor R4; and the emitter-follower circuit 4 made of an emitter-follower transistor Q6, pull-down transistor Q7, and emitter-follower resistor R5. The base of pull-down transistor Q5 is connected to the collector of the transistor Q1 via a capacitor C1, whose signals are inversed in phase to the signals applied to the base of the emitter-follower transistor Q4. Similarly, the base of the pull-down transistor Q7 is connected to the collector of the transistor Q2 via a capacitor C2, whose signals are inversed in phase to the signals applied to the base of the emitter-follower transistor Q6. Note, numerals 11 and 12 denote the input terminals where input signals Vin1 and Vin2 are input, and 13 and 14 denote the output terminals from which the output signals Vout1 and Vout2 are output. Vcs1 is the control voltage, GND the high potential power source (positive power source), and V.sub.EE1 the low potential power source (negative power source).
For instance, at the NOR logic output in the above construction, if Vin1 is at a lower level "L" than Vin2, Q1 is off and Q2 is on, with Q1's collector potential (S NOR) being at a low potential level defined as the positive power source (GND) minus the voltage drop across R1. If Vin1 changes from "L" to "H", SNOR changes from a low potential to a high potential near GND.
In this case, the NPN transistor Q5 is usually on when sending the output level from the output terminal 13, and when Q5 changes, its current flow is instantaneously increased by the current flowing through the capacitor C1. The same operation occurs in the transistor Q7. In other words, in the active pull-down ECL circuit 1, the control voltage V cs1 is always applied to the bases of Q5 and Q7 to turn them on in order to produce the output level. Only when Q5 and Q7 are changed is the current flowing through them increased by the current momentarily flowing through the capacitors C1 and C2 (which block DC) to improve the load driving force. Then the charges are promptly discharged from the wiring load capacitance CL via Q5, resistor R4, Q7, and resistor R5 to switch from the level H to the level L at high speed.
In this conventional active pull-down ECL logic circuit, however, Vcs1 must be applied to the transistors Q5 and Q7 at all times to keep them turned on, which results in increased power consumption, making it necessary to increase the transistor size. The increased junction and wiring capacity can obstruct high speed operation while the increased gate size prevents high integration of transistors.
Other methods to solve the above problem are disclosed in the U.S. Pat. No. 4,539,493 in which, in the two output circuits used in the ECL logic circuit, the bases of the pull-up transistors in these output circuits are connected to each other via a capacitor. The base of the pull-up transistor of one output circuit is connected to the base of the emitter-coupled transistor of the other output circuit, and the base of the pull-up transistor of the other output circuit is connected to the emitter of the emitter-coupled transistor of the other output circuit. However, these prior arts cannot overcome the drawback that a capacitance C is added to the current switch causing a delay in switching operation of ECL, and that the pull-down transistor Q5 is always on, resulting in large power consumption.